1. Field of the Invention
The present invention relates generally to methods for fabricating embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention related to methods for fabricating, with enhanced performance, embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Common in the art of semiconductor integrated circuit microelectronic fabrication is the use of embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications that simultaneously incorporate logic semiconductor integrated circuit microelectronic fabrication devices (typically including, but not limited to, field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication devices) and dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication devices (typically including, but not limited to, field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication devices in conjunction with storage capacitor memory semiconductor integrated circuit microelectronic fabrication devices).
Embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications are particularly useful within semiconductor integrated circuit microelectronic fabrication applications that require both the storage and the timely manipulation of comparatively large quantities of digital data. Such applications often include, but not limited to, digital computer graphics applications.
While embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications are thus desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is known in the art of semiconductor integrated circuit microelectronic fabrication that embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications are often difficult to efficiently fabricate with enhanced performance, insofar as the performance characteristics of logic semiconductor integrated circuit microelectronic fabrication devices within embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications are affected by different semiconductor integrated circuit microelectronic fabrication processing considerations in comparison with the performance characteristics of memory semiconductor integrated circuit microelectronic fabrication devices within embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications.
It is thus desirable in the art of embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication to provide methods and materials that in turn provide embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications having desirable properties, and methods for fabrication thereof, have been disclosed within the art of semiconductor integrated circuit microelectronic fabrication.
For example, Sung, in U.S. Pat. No. 5,858,831, discloses a method for forming, with both enhanced performance and enhanced manufacturing economy, an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method employs only a single additional photolithographic masking step for forming, in part, within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device having formed therein a comparatively thinner gate dielectric layer in comparison with a gate dielectric layer formed within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication.
In addition, Wu et al., in U.S. Pat. No. 5,998,251, similarly also discloses a method for forming, with both enhanced performance and enhanced manufacturing economy, an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method provides for forming in part simultaneously within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication a conductor interconnect layer within a logic device region within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication and a storage capacitor within a memory device region within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication.
Finally, Liao, in U.S. Pat. No. 6,069,037, similarly yet also discloses a method for forming, with both enhanced performance and with enhanced manufacturing economy, an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method comprises a self-aligned method which employs a pair of photoresist masking steps, only one of which requires a critical dimensional tolerance, to form within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device having formed therein a comparatively thinner gate electrode in comparison with a gate electrode employed within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device within the embedded dynamic access memory (DRAM) semiconductor integrated circuit microelectronic fabrication.
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials that may be employed for fabricating, with enhanced performance, embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication is fabricated with enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication. To practice the method of the present invention, there is provided a semiconductor substrate. There is then formed upon a first portion of the semiconductor substrate a first gate dielectric layer in turn having formed thereupon a first gate electrode, where the first portion of the semiconductor substrate is separated from a second portion of the semiconductor substrate having formed thereupon a second gate dielectric layer in turn having formed thereupon upon a second gate electrode. There is also formed within the first portion of the semiconductor substrate and separated by the first gate electrode a pair of first source/drain regions. Similarly, there is also formed within the second portion of the semiconductor substrate and separated by the second gate electrode a pair of second source/drain regions. Finally, there is also formed contacting one of the pair of second source/drain regions a storage capacitor, wherein the pair of first source/drain regions is formed after forming contacting the one of the pair of second source/drain regions the storage capacitor.
Within the present invention: (1) the first portion of the semiconductor substrate comprises a logic device region of the semiconductor substrate having formed thereupon a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device; and (2) the second portion of the semiconductor substrate comprises a memory device region of the semiconductor substrate having formed thereupon a field effect transistor (FET) memory semiconductor integrated microelectronic fabrication device in conjunction with the storage capacitor.
There is provided by the present invention a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication, wherein the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication is fabricated with enhanced performance. The present invention realizes the foregoing object by forming, when fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication, a storage capacitor contacting one of a pair of second source/drain regions which is separated by a second gate electrode, prior to forming a pair of first source/drain regions separated by a first gate electrode, further wherein the pair of first source/drain regions is employed within a field effect transistor (FET) logic semiconductor integrated circuit microelectronic device within a logic device region of a semiconductor substrate from which is fabricated the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication and the pair of second source/drain regions is employed within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device within a memory device region within the semiconductor substrate from which is fabricated the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication. By employing within the context of the present invention the foregoing order of fabrication, performance of the field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication is enhanced insofar as a pair of first source/drain regions from which is comprised the field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device is not exposed to temperature excursions and additional processing incident to forming the storage capacitor contacting the one of the pair of second source/drain regions from which is comprised the field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device within the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are otherwise generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific ordering to provide the present invention. Since it is thus a specific ordering of methods and materials that provides at least in part the present invention, rather than the existence of specific methods and materials that provides the present invention, the method of the present invention is readily commercially implemented.